Video: Identifying Equivalent Logic Gates

Which of the following pairs of logic gates produces the same output as a NAND gate? [A] Gate A [B] Gate B [C] Gate C [D] Gate D

03:39

Video Transcript

Which of the following pairs of logic gates produces the same output as a NAND gate?

Now we’ve been given four options here, A, B, C, and D. However, instead of going through all of these options and working out if they behave like a NAND gate, let’s first consider what a NAND gate actually does. Now a NAND gate, or a NOT AND gate, basically displays the opposite behavior to an AND gate. More specifically, a NAND gate displays the inverted behavior to an AND gate. So, what do we mean by this?

Well, an AND gate behaves according to the following truth table. It has two inputs, inputs A and B, and one output. Now if the two inputs are set to zero, then the output is zero as well. If input A is set to zero and B to one, then the output is still zero. If input A is one and input B is zero, then the output is, yet again, zero. But if both inputs are set to one, then the output comes out as one. In other words, the output for an AND gate can only be one if input A and input B are set to one. This is why it’s known as an AND gate.

But as we’ve already said, a NAND gate, which is what we’re trying to work out here, displays inverted behavior to an AND gate. So, a NAND gate, or a NOT AND gate, basically takes all the output values from an AND gate and reverses them.

So, in the first instance, when input A and input B are both zero for an AND gate, the AND gate produces an output of zero. So, in the same situation, input A and input B are zero, the NAND gate produces the opposite output. It produces a one instead. Similarly, for when input A is zero and input B is one, the AND gate produces a zero. But in the same scenario, the NAND gate produces a one. And this is true for every situation.

The AND gate in this situation produces a zero, but the NAND gate produces a one. And, once again, in the final instance, when both inputs are one, we get a one from the AND gate. But when both inputs to the NAND gate are one, we get a zero instead. In other words, we can think of a NAND gate, or a NOT AND gate, as an AND gate with its output reversed, or inverted.

At this point, we can recall then that a NOT gate is known as an inverter. Because a NOT gate only has one input and one output. Whatever we put in as an input to the NOT gate, the output is the opposite. In other words, a NOT gate behaves according to the following truth table. If the input is zero, then the output is one. And if the input is one, then the output is zero. It basically flips the input to give us the output.

So at this point, we can see then that if we want to produce a NAND gate from two separate gates, then what we can do is to take an AND gate and then stick a NOT gate right after it to flip the result. This way, let’s say we set the inputs of the AND gate to zero and zero in both cases, then the AND gate will produce an output of zero. But the NOT gate stuck right after it would take that zero as its input and produce a one. And those two effects combined is basically the same thing as having an input of two zeros for a NAND gate and an output of one.

And if we follow this logic through, we’ll see that it is true for all input and output variations. In other words, an AND gate followed by a NOT gate displays the same behavior as a NAND gate. So, all that’s left for us to do now is to look through options A to D and see which one consists of an AND gate followed by a NOT gate.

Well, the option that we’re looking for is option D. Because we can see that this is the symbol for an AND gate, which make sense because you’ve got one- two inputs and one output. And then the output from the AND gate becomes an input for the NOT gate, which is this symbol. And hence, the NOT gate is going to flip the result in whatever the output of the AND gate is. Thus, producing altogether a NAND gate. Hence, we can say that the pair of logic gates that produces the same output as a NAND gate consists of an AND gate followed by a NOT gate.

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