### Video Transcript

The diagram shows a NAND gate where a single signal from the circuit is used for both inputs of the NAND gate. The truth table shows the different possible inputs of this arrangement.

So, before we read the rest of the question, let’s quickly take a look at this setup. We can see first of all that we’ve got a NAND gate. However, normally, NAND gates have two inputs. But in this case, we can see that both inputs of the NAND gate are fed into from the same point. In other words, this input signal is split into two.

And in other words, what we are restricting ourselves to here is that both the inputs of the NAND gates will have the same value. They will either be both zero if this input is zero, or they will be both one if this input is one. And we’ve been given a table here that shows us the value of the input either zero or one, as well as the value of the output in each case, 𝑝 or 𝑞. Now, we’re going to need to find these values.

Specifically looking at the questions asked of us, we can see that the first question states, what is the value of 𝑝 in the table? And the second question states, what is the value of 𝑞 in the table?

So, let’s go about finding the values of 𝑝 and 𝑞. We’ll come back to this question in a second. Now, to find the values of 𝑝 and 𝑞, let’s start by recalling what the truth table for a conventional NAND gate looks like. And when we say conventional NAND gate, we mean when the inputs are independent from each other. Not like what we have here.

So, here is the truth table for a NAND gate, assuming independent inputs. We’ve called these inputs A and B. And based on these values of A and B, we can see what the output would be. Now, a simple way to memorize the truth table for a NAND gate is to think of a NAND gate as a NOT AND gate. And then, we remember that an AND gate is a gate which only ever gives an output of one if both the inputs are also one. In any other circumstance, in other words if any of the inputs is zero, then the output automatically becomes zero for an AND gate. And then, what turns an AND gate into a NAND gate is the NOT part, where a NOT gate takes whatever the output is and inverts it.

In other words, if we just had an AND gate, then the truth table would look like this. We’d have three zeros and then a one. And the output only be one for an AND gate if both the inputs were one as well. But then a NAND gate takes all of these inputs and inverts them. So, all the zeros become ones, and all the ones become zeros. And that’s how we can recall the truth table of a NAND gate.

But anyway, so in this particular circumstance, what we’ve done is we’ve restricted ourselves slightly. The two inputs to the NAND gate are no longer independent from each other. They both now must be the same value because they’re both being fed from the same input. And so, we take this conventional NAND gate truth table, and we only look at the rows where both of the input have the same value. In other words, when input A and B are both zero or when input A and B are both one. And those input values then become the value of the input here.

So comparing this truth table to this truth table, we can see that when the two inputs of the NAND gate are both zero, in other words when this input is zero, then our output must be one. And so we can see that when the input is zero, the output must be one. And hence, the value of 𝑝 must be one. So that’s our answer to the first part of the question.

And then looking at the second part, when both inputs A and B are one, in other words when this input is one, and so we are looking at this column of this truth table. Then we see that the output is zero. And hence, the value of 𝑞 must be zero as well. So that’s are our answer to the second part of the question.

So all in all, our truth table now says that when the input is zero, the output is one. And when the input is one, the output is zero. And the final part of the question asks us what type of logic gate is this arrangement equivalent to.

In other words, this arrangement here where the two inputs to the NAND gate are fed from the same input, we need to find a logic gate that this is equivalent to. And we can do this using this truth table. We can see that when the input to this arrangement is zero, the output is one. And when the input is one, the output is zero. In other words, the input gets inverted to produce the output. And hence, this particular arrangement is equivalent to an inverter logic gate, otherwise known as a NOT gate.